FIG. 3 shows a portion of a prior art high frequency amplifier utilizing a GaAs field effect transistor (hereinafter referred to as GaAs FET). In FIG. 3, as signal terminals, there are provided an input terminal 1, an output terminal 2, a drain bias terminal 3, and a gate bias terminal 4. As striplines, there are provided an input section stripline 10, an output section stripline 8, and a gate bias stripline 6. An output matching condenser 9 is provided at the other end of the output section stripline 8. A GaAs FET 14 is a main amplification FET. A first, second, and third gate bias resistor 11, 12, and 13 constitute a gate bias circuit of the main amplification FET 14.
The respective circuit elements are connected as shown in FIG. 3 and this circuit is a high frequency amplifier operating as follows.
A drain voltage is applied to the GaAs FET 14 from the drain bias terminal 3 through the drain bias stripline 7, and a gate bias voltage is applied to the GaAs FET 14 from the gate bias terminal 4 through the gate bias resistors 11, 12, and 13 and the gate bias stripline 6. In this state, when a high frequency signal is input to the input terminal 1 of the amplifier, a signal amplified by the amplifier is supplied to the output terminal 2.
FIG. 4 shows an input/output (input power vs. output power) characteristic for the operation of this high frequency amplifier. The abscissa represents input signal level P.sub.in, the left ordinate represents output signal level P.sub.out, the right ordinate represents power addition efficiency .eta..sub.add and the drain current I.sub.D. The solid line in the graph represents the input signal level P.sub.in vs. output signal level P.sub.out characteristic, the dotted line represents the input signal level P.sub.in vs. power addition efficiency .eta..sub.add characteristic, and the dot-dash line represents the input signal level P.sub.in vs. drain current I.sub.D characteristic, respectively, of the FET 14. Furthermore, ##EQU1## (herein, V.sub.D represents the source to drain voltage).
In the prior art high frequency amplifier of such construction, when the input signal level P.sub.in is low in A-class amplification operation, the efficiency .eta..sub.add is unfavourably lowered. That is, the linear gain G.sub.LP is represented by ##EQU2## and the above described formula (1) can be rewritten as the following: ##EQU3## Because the gate bias voltage is constant, the drain current I.sub.D and drain voltage V.sub.D take approximately constant values. Further, the gain G.sub.LP takes a constant value. Therefore, the above described formula (1)' is represented by EQU .eta..sub.add .perspectiveto.k'.multidot.P.sub.in
(herein, k' is a constant, and V.sub.D and I.sub.D are constants). As shown in FIG. 5, the power added efficiency .eta..sub.add is proportional to the input signal level P.sub.in. Accordingly, in case where the input level P.sub.in is low, idle DC power does not contribute to the high frequency and is dissipated, thereby lowering operating efficiency.